Both Barcelona and Nehalem are chip multiprocessors (CMPs), having multiple cores and their caches on a single chip. CMP onchip L2 cache design has interesting tradeoffs. The following table shows the miss rates and hit latencies for two benchmarks with private vs. shared L2 cache designs. Assume L1 cache misses once every 32 instructions.
Which cache design is better for each of these benchmarks? Use data to support your conclusion.